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Curriculum Vitae

Personal Data
First name Albert
Last name Moreno Forrellad
Position Support to projects/web
Date and Place of birth 1972, Barcelona
Country Spain
Telephone +34 93 59 29 966
Mobile E-mail amoreno ( at ) matgas.com
Office 3-10 Letter Box 17

Academic Information
Degree University
Electronic Engineering UPC (ETSETB)
Industrial-Automation Technical Engineering UPC (EUETIT)

Complementary Studies
Formation Centre / Description
6th EELA Tutorial (User and System Administrators) Madrid 2006
International Summer School on Grid Computing Ischia (2006)
JAVA2 Certified Programmer for J2EE (CX-310-035) Id-Form, Geneva (2005)
JAVA2 Certified Web Component Developer for J2EE (CX-310-081) Id-Form, Geneva (2005)
MCAD, Microsoft Certified Application Developer (070-316) (070-315) (070-320) Id-Form, Geneva (2005)
PrimeTime course by Synopsys, Geneva (2003)
Basic Chip Synthesis, Design Compiler course by Synopsys, Geneva (2003)
Advanced Digital System EPFL, Lausanne (2002)
Arm9/11 course by Motorola, Geneva (2002)
Clearcase course by Motorola, Geneva (2002)

Work experience
Description
ICMAB, Barcelona (Abr 2005 - Nowadays) IT responsable for all software of an european virtual scientic community. Administration and managing of all tipical tools of and intranet, including provide, install, test and adaptation of the software. it also includes prepare documentation and tutorials. Responsible to improve the data acquisition, monitoring and processing of several institute experiments, both in hardware and software side. Technical adviser when new electronic devices are acquired by the institute, installation and its implementation. Study and planning of a GRID implementation using the clusters of the institute, development of all scripts and procedures necessary for optimizing simulations and calculus of the theoretic department. Study and planification of a project for a Grid implantation in our institute and a project for being a Certification Authority.
Consultant & Independent programmer (Mar 2004 - Mar 2005)
MOTOROLA, Geneva, Switzerland. (Mar 2001 - Jan 2004) IC Design Engineer, Wireless Systems Group. Low Power - Deep exploration and analysis of RAM memories. Design of a testcase from scratch experiment with different Architectures and memories communications. Analyse results and propose techniques lowering its power consumption. Develop and optimise of all scripts for synthesis and for handle its techniques. Worked on European project with Polytecnico Torino on RTL power estimation and Low Power Architecture. STA (Static Timing Analysis) - Creation and running of different mode analysis for a platform, check all exceptions are valid and approved. Fix and propagate constraints from sub-modules to top. Clock tree analysis. Model by using Esterel the behaviour of some sub-modules in order to improve its performance.
CERN (European Laboratory for Particle Physics), Geneva, Switzerland. (Oct 1999 - Dec 2000) Technical Student Program at CERN. Realising a complete work consisting in the design of a bridge between G64 bus and Profibus-DP field-bus. Including the design of the hardware and both the FPGA software and the SCADA software to control the exchange of data between these buses. Published the paper "Profibus-DP to G-64 Configurable Interface".

Curriculum on pdf format
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